1. Field of the Invention
The present invention relates to a memory component and the addressing of memory cells therein for the replacement of defective memory cells.
2. Description of the Related Art
The miniaturization of integrated semiconductor circuits and in particular of memory components is increasingly reaching physical and economic limits. Every further reduction of the dimensions of memory cells necessitates a very high technological outlay, for example for introducing dielectrics having a high dielectric constant or permittivity for the storage capacitors. It is already customary for the introduction of a new dynamic random access memory (DRAM) shrink (i.e., reduction of the linear dimensions) to necessitate an increase in the technological costs by 10% to 15%. This offsets a large proportion of the cost advantages resulting from the shrink, which are typically 20% to 30%.
The reason for the increase in the technological costs for every shrink or from generation to generation is that the capacity of the individual memory cell is typically kept essentially constant from generation to generation. As a result, on an individual DRAM memory chip, on average statistically there are always 50 to 100 individual memory cells to be repaired owing to a defect, by said memory cells being replaced by redundant memory cells. However, it is becoming increasingly difficult to keep constant this number of defective memory cells to be repaired per DRAM memory component.
Therefore, a paradigm shift is proposed. By providing massive redundancy, that is to say, a substantially higher number of redundant memory cells in comparison with conventional memory components, the requirements made of the individual memory cell can be greatly reduced. This in turn permits a reduction of the electrostatic capacitance of the individual storage capacitor, for example, by 50% or more. Massive redundancy requires an additional chip area. However, this additional chip area generates lower fabrication costs than the high technological outlay described above.
However, the conventional repair of defective or weak memory cells is not suitable for a very high number of defective memory cells and corresponding massive redundancy. A memory component is conventionally organized in memory blocks. Each memory block has a regular region with regular memory cells and a redundant region with redundant memory cells. Defective regular memory cells of a memory block are replaced by redundant memory cells of the same memory block.
In this case, it inevitably happens that individual memory blocks have only very few defective memory cells, with the result that the redundancy present is also only partly utilized. At the same time, other memory blocks may, under certain circumstances, have so many defective memory cells that they can no longer be completely replaced by the redundancy present. If each memory block is provided with so much redundancy that all defective memory cells can be repaired with a predetermined high probability, superfluous redundancy is inevitably present in many memory blocks. This means a waste of chip area and hence unnecessarily high fabrication costs.
Normally, each memory block is assigned two word line address decoders. A first address decoder activates the assigned word line depending on a word line address. A second decoder is connected to an address memory or has an address memory in which the word line addresses of defective memory cells are stored. If the second decoder receives a word line address which is also stored in the address memory, it deactivates the first decoder and activates a redundant word line whose address is assigned to the word line address of the defective memory cell.
Each memory block conventionally has only a small number of redundant word lines. The address memory is correspondingly small. However, the concept described cannot readily be applied to a memory component which comprises a significantly larger number of redundant memory cells and redundant word lines in each memory block. In particular, arranging a large address memory in direct proximity to each memory block is problematic.